One of the killer features of the Xilinx FPGA’s used in the Papilio Boards are the DCM’s (Digital Clock Manager). The DCM’s allow you to take the incoming 32Mhz clock from the external oscillator and generate any speed clock that you want! Even better, you get four DCM’s so you can generate four completely independent clocks all running at whatever frequency you desire. The DCM’s are so powerful they can even be used as the base for a nice frequency generator as outlined in this reference design by Ken Chapman.
Many open source designs on the Internet have been written for evaluation boards that use an external 50Mhz clock, but a 50 Mhz clock is right on the edge of what is considered a high speed design. The Papilio One purposely uses a slower 32Mhz clock that is not considered high speed and is better suited for a double layer circuit board. It makes sense to keep high speed signals inside the FPGA and off the circuit board when possible. This tutorial shows how to convert the 32Mhz clock to the required 50Mhz clock and keep the high speed 50Mhz clock internal to the FPGA which sidesteps any high speed Signal Integrity issues such as reflection, crosstalk, or ringing.