Overview
zpuino-1.0-PapilioOne-S3E500-LogicStart is a ZPUino variant for the LogicStart MegaWing on the Papilio One 500K.
Source Code
Peripherals
| Name | WingSlot | Notes |
| ZPUino_SPI | 0 | |
| ZPUino_UART | 1 | |
| zpuino_gpio | 2 | |
| zpuino_timers | 3 | |
| zpuino_sigmadelta | 5 | |
| zpuino_spi | 6 | |
| zpuino_crc16 | 7 | |
| zpuino_vga | 9 | Hardwired to LogicStart pins |
| wb_char_ram_8x8_sp | 10 | Character ROM for VGA core |
| zpuino_io_YM2149 | 11 |
PPS
(:source:)
gpio_spp_data(0) <= sigmadelta_spp_data(0); -- PPS0 : SIGMADELTA DATA
gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
gpio_spp_data(5) <= sigmadelta_spp_data(1); -- PPS5 : SIGMADELTA1 DATA
gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
gpio_spp_data(8) <= sid_audio;
spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
(:sourceend:)